The present invention relates to peak detection circuits, and more particularly to a wholly differential CMOS peak detection circuit that provides improved linearity, better noise immunity and less sensitivity to process variations.
Glitches and noise spikes are a common cause of problems in both analog and digital circuits. Modern oscilloscopes, such as digital storage oscilloscopes (DSO), need to be able to capture these narrow pulses to be useful in troubleshooting such circuits. Also such pulses may be as narrow as two nanoseconds (2 ns), which can trigger TTL circuitry, so the DSO needs to be able to obtain at least one sample of such a spike. When the time base of the DSO is adjusted so that the input signal is highly undersampled, the period between samples may be greater than the width of such spikes. Therefore the spikes may rarely or never be sampled. As a result peak detectors have been placed in the signal acquisition circuitry between the input and a digital sampler. In this way the minimum and maximum of the input signal within a specified time window is detected and held until they can be sampled or converted by an analog-to-digital converter (ADC).
An example of a prior art peak detector using bi-polar technology is present in the Tektronix 2430 DSO, manufactured by Tektronix, Inc. of Beaverton, Oreg., United States of America. The input signal is split into two opposite polarity signals that are fed into two positive and two negative peak detectors to allow detection of either positive or negative spikes. By using two peak detectors for each polarity, one can be peak detecting while the other is either holding for sampling or tracking. The peak detectors in this configuration peak detect for two intervals, hold for one interval and track for another interval before repeating the cycle, where two intervals are equal to a sample period. Each peak detector has an output stage for amplification prior to the sampling circuitry.
A peak detect cell for the Tektronix 2430 DSO is shown in FIG. 1 in the form of a simple unity gain feedback amplifier with a wide bandwidth. Transistors Q1-Q4 form a differential amplifier with a current source load I1. The output of the differential amplifier is fed back to the input through diode D and transistors Q5, Q6. When control signals S1, S2 are both low, the peak detector is in the detect mode. If the input signal Vin is greater than the output signal Vout, then capacitor C charges until Vin equals Vout. However if Vin is less than Vout, then diode D prevents the capacitor C from discharging so that Vout maintains the most positive value of Vin.
At the end of the detection period, the output signal is held and further inputs are ignored so that Vout may be sampled. At this point control signal S2 is high while S1 is still low to disconnect the input from the output. After Vout is sampled, control signal S2 is lowered and S1 is raised so that the diode D is bypassed while the input signal is enabled, and the capacitor is allowed to charge or discharge to track the input signal Vin. However bi-polar technology is relatively expensive and uses relatively high power, there is base current leakage from the storage capacitor C, there is a large offset due to the Darlington differential pair, there is no clamp of transistor Q3 (with the potential of saturation), there is excess delay around the closed loop (with the potential of ringing), and the circuit is single ended.
A CMOS based peak detector is disclosed in U.S. patent application Ser. No. 07/844,089, filed on Mar. 2, 1992 by Grigory Kogan and entitled "CMOS-BASED PEAK DETECTOR FOR FAST-IN, SLOW-OUT MIN/MAX DETECTION." CMOS technology is less expensive, more dense and uses less power than comparable bipolar technology, but is slower and must be configured differently to achieve high bandwidth operation. Referring to FIG. 2 two nodes A, B of a CMOS peak detector cell are coupled to a voltage rail Vdd during a precharge interval, after which they are disconnected. An acquire signal controls a switch Q1 that connects one node A to an input signal Vin, the one node being connected to the other node B by a transistor Q4 so that the capacitance C at the other node tracks the voltage at the first node. At the end of the acquisition interval the first node A is disconnected from the input signal Vin and the voltage on the other node B is held for transfer via a buffer amplifier AO to a sampler. Following transfer a clear signal connects the other node B to the voltage rail Vdd in preparation to repeat the cycle. However this circuit is relatively slow, the source follower Q4 has no current source so that point B dribbles down to one V.sub.T above point A producing a long tail, and the circuit is single ended.
What is desired is a CMOS peak detector circuit that is fully differential to provide the advantages of both differential circuitry and CMOS technology in a peak detector.